Integrated circuit (IC) structures have middle of the line (MOL) contacts that connect field effect transistors (FETs) to back end of the line (BEOL) metal levels. The MOL contacts include at least one gate contact (also referred to herein as a CB contact) and source/drain contacts (also referred to herein as CA contacts). Each gate contact extends vertically through the interlayer dielectric (ILD) material from a metal wire or via in the first BEOL metal level (also referred to herein as the M0 level) to the gate of the FET. Each source/drain contact extends vertically through the ILD material from a metal wire or via in the first BEOL metal level to a metal plug (also referred to herein as a TS contact), which is above and immediately adjacent to a source/drain region of the FET. Conventional techniques for forming these MOL contacts inherently include risks of the following: (a) opens (also referred to herein as voids) occurring between the first BEOL metal level and both the source/drain contacts and the gate contact; (b) shorts occurring between the gate contact and a metal plug, particularly, if the gate contact is to be formed on a portion of the gate above the active region of the FET (i.e., particularly, if the gate contact is a gate contact over active, also referred to herein as a CBoA) in order to allow for size scaling; and (c) shorts occurring between the source/drain contacts and the gate. Thus, there is a need in the art for an improved method of forming an IC structure with MOL contacts in a manner that avoids the occurrence of the above-described opens and shorts.